An FPGA implementation of a multi-comparand multi-search Associative Processor / Zbigniew Kokosiński, Wojciech Sikora // W: Field-Programmable Logic and Applications : Reconfigurable Computing is Going ... więcej

An FPGA implementation of a multi-comparand multi-search Associative Processor / Zbigniew Kokosiński, Wojciech Sikora // W: Field-Programmable Logic and Applications : Reconfigurable Computing is Going Mainstream : 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002 : proceedings [Dokument elektroniczny] / eds. Manfred Glesner, Peter Zipf, Michel Renovell. – Berlin ; Heidelberg : Springer, 2002. – (Lecture Notes in Computer Science ; 2438). – S. 826-835 : rys., tab. – Tryb dostępu: https://link.springer.com/chapter/10.1007/3-540-46117-5_85. – Bibliogr. 28 poz., Abstr. – doi: 10.1007/3-540-46117-5_85. – ISBN 978-3-540-46117-3 (online). – ISBN 978-3-540-44108-3 (print)

The multi-comparand associative search paradigm is shown to be efficient in processing complex search problems from many application areas including computational geometry, graph theory, and list/matrix ... więcej

The multi-comparand associative search paradigm is shown to be efficient in processing complex search problems from many application areas including computational geometry, graph theory, and list/matrix computations. In this paper the first FPGA implementation of a small multi-comparand multi-search associative processor is reported. The architecture of the processor and its functions are described in detail. The processor works in a combined bit-serial/bit-parallel mode. Its main component is a multi-comparand associative memory with up to 16 programmable prescription functions (logic searches). Parameters of implemented FPGA devices are presented and discussed.